1. Field of the Invention
The present invention relates to a semiconductor device in which a source/drain is formed into two-layer structure having shallow and deep junctions, and a manufacturing method thereof.
2. Description of the Related Art
Recently, it has become valued to reduce the standby power of a semiconductor chip, with the wide use of a cellular phone, a PDA (personal digital assistants) and the like. As a direct method for reducing the standby power of the semiconductor chip, it is known to reduce the off-state current (Ioff) of a transistor. In the concrete, since a high threshold voltage (Vth) achieves low Ioff, the dose of ion implantation for forming pocket regions, which are provided to improve the roll-off characteristics of the threshold voltage (Vth) and current drive capacity, and for controlling Vth is increased for the purpose of obtaining high Vth.
Patent document 1: Japanese Patent Application Laid-Open No. 2003-31798.
Patent document 2: Japanese Patent Application Laid-Open No. 6-224381.
A highly scaled transistor having short gate length (Lg), however, has an abrupt junction and high channel impurity concentration. Thus, increase in the dose of ion implantation for forming the pocket regions and controlling Vth can increase Vth, but also increase the leak between a body (a substrate and a semiconductor region) and a drain. As a result, there is a problem that Ioff is increased.
This situation will be described with reference to FIGS. 11 and 12.
FIG. 11 is a schematic sectional view of a transistor which explains the current components of Ioff. Ioff is expressed by the sum of the leak between the gate and a drain (GD leak), the leak between a source and the drain (SD leak), and the leak between a body and the drain (BD leak). FIG. 12 shows variation in the gate voltage-drain current (Vg-Id) characteristic of transistors having a gate length of 80 nm, when the dose of ion implantation for forming the pocket regions is increased.
Vth increases as the dose for forming the pocket regions increases. When the dose exceeds a certain value, however, Ioff depends on the BD leak due to increase in the BD leak, so that Ioff is minimized before the certain value. If the BD leak is restrained without varying Vth of the transistor, as shown in FIG. 13, it becomes possible to actualize lower Ioff.
Ordinary, phosphorus (P+) is used for forming the extension regions (or an LDD layer), in order to reduce the BD leak of an n-type MOS transistor. In this method, however, since the diffusion of P+ is large, Vth decreases in the transistor having a short gate length, so that Ioff does not become lower.